Resume

🎓 Education

College of Engineering Honors Program

GPA: 3.89

Sept. 2019 - Jun. 2023

Designed and implemented a microservice API in Java Spring that provides users with finer control over their account’s capabilities, e.g. payment types accepted by a merchant.
Documented UML class diagrams, sequence flow diagrams, and API specs on Swagger to collaborate with clients.
Competed in a 48-hour hackathon with 3 teammates leading to inter-organization recognition for the project and senior leadership’s encouragement to apply for a patent internally.

Jun. 2022 - Sept. 2022 ~ San Jose, CA

Applied systems engineering principles to select and deploy a ~$100k-$200k software system that collects, stores, and analyzes data from optics fabrication & recycling machines for NIF.
Interviewed 30 stakeholders of engineers, managers, technicians, and cybersecurity experts to collect requirements.
Developed system requirements, architectures, and a concept of operations (CONOPs) to capture the deployment configuration and end-user experience.

Jun. 2021 - Jun. 2022 ~ Livermore, CA

Designed a schema for a SQL database to replace the legacy Excel-based data management system.
Prototyped a GUI and REST API with Python to automate managing data, performing computations, and generating formatted spreadsheets.
Kicked off development for a production web application with a Java Spring REST API and front-end to add the application to the lab-wide internal web app suite, improving client-side accessibility.
Developed Splunk dashboards to use probabilistic methods to identify and highlight outliers in data.

Jun. 2020 - Jun. 2021 ~ Livermore, CA

Developed microcontroller firmware based on Zephyr RTOS to interface with peripherals that collects vehicle diagnostic data, fetches GPS data, and uploads the marshalled UDP datagram over LTE-M.
Designed the PCB layout for a 4-layer custom PCB including on-board RF circuitry (LTE-M & GPS).
Implemented & deployed a front-end, API, and UDP server on AWS.

Ported a Linux kernel driver for a modern kernel (6.2) and leveraged buildroot to integrate it into the build process for Cohort 🔗, a novel software-hardware queue interface to better leverage heterogeneous hardware accelerators.
Debugged RTL & Vivado configurations to boot the OpenPiton+Ariane 🔗 open-source RISC-V processor with a modern Linux kernel (6.2) on a Digilent Genesys 2 FPGA, providing a working baseline for Cohort’s release.

Improved a custom Python command line debugging utility to support calibration & tests for the microcontroller.
Documented the implementation of STM32 C++ HAL to make code accessible for new developers.
Automated dead link detection in continuous integration for repository maintainability.